1. Field of the Invention
The invention relates in general to memory devices, and in particular to multi-bits per cell memory arrays that provide high density and compactness.
2. Background of the Invention
Flash based electrically erasable and programmable read only memories (EEPROMS) are re-programmable, non-volatile memories that have become ubiquitous in a variety of computer systems for storing data. These computer systems can include traditional desktop and laptop computer systems, as well as portable computer systems, such as cellular telephones, Personal Digital Assistance (PDAs), and other portable communication systems. The typical data storage element of an EEPROM is a floating gate transistor, such as a field effect transistor (FET) having an electrically isolated, or floating gate that controls electrical conduction between source and drain regions. Data is represented by charges stored on the floating gate and the resulting conductivity obtained between source and drain regions.
The requirements of conventional flash memory devices, both with regard to physical size and density continuously grow more stringent. There is also continued pressure to lower the costs of conventional flash memory devices. It has been shown that as the density of conventional flash memory devices increases, and/or as the cost of conventional flash memory devices is reduced, the market for conventional flash memory devices grows. For example, as the price of conventional price memory devices goes down, new applications for flash memory devices emerged. The increase demand caused by increased density and lower prices further drives requirements for smaller, more dense, and less expensive flash memory devices.
Conventionally, cost reduction and density increase for flash memory devices have been achieved through process scaling in the same manner as other types of semi-conductor memory devices. In other words, as the ability of semi-conductor manufacturing process equipment improves, smaller features can be resolved on a silicon wafers resulting in a smaller memory cell and thus more bit in a given amount of silicon area. More bits in a given silicon area result in higher density memories and lower costs per bit. Using the technique of process technology scaling, conventional flash memory device cell size has been reduced significantly over the past 10 to 20 years.
Process scaling typically affects the size of the transistor comprising a memory cell. Specifically, scaling often reduces the gate and the channel lengths for the cell transistor. A point is reached, however, where the gate and the channel lengths cannot be reduced beyond a critical value without increasing the parasitic source/drain junction capacitance of the device, which results in adverse effects, referred to as short channel effects. Short channel effects can include hot carrier damage and the possibility of punch through between the source and drain regions, which would have an adverse effect on the device performance. Thus, process scaling has limits in terms of the increase in density that can be achieved. Moreover, increase scaling can have an adverse effect on devise performance.
One way to improve device performance is to reduce the junction capacitance for the cell transistor. To reduce the junction capacitance, the channel length has to be large enough to avoid short channel effects but clearly, a larger channel length would limit the size reduction, or scaling, that can be achieved for the cell transistor. As a result, scaling and device performance objectives are often at odds. These competing objectives further limit the benefits that can be achieved by scaling.
Multi-Level Charge (MLC) techniques have been devised that can further increase density gains and size reductions beyond that which can be achieved using scaling. MLC techniques take advantage of the ability to store multiple charge levels in the floating gate of a transistor cell. Each of these different levels can then be used to represent multiple bits within the cell. Thus, each cell can store more bits which increases the density and reduces the physical size.
Still, conventional applications for flash-based memory devices require further increases in density and reductions in size and cost. New techniques must be developed to address the requirements of the increasing number of new applications.